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em 47 fm16 88 mca/sca 8 gb ( 3 2 m 8 bank 16 2 rank ) double data rate 3 sdram features ? use two 256 m x 16 dies stack to 256 m x 16 x 2 r ddp . ? vdd/vddq = 1.35v - 0.065/+0.1v ? backward compatible to vdd/ vddq = 1.5v 0.075v. ? all inputs and outputs are compatible with sstl_15 interface. ? fully differential clock inputs (ck, /ck) operation. ? eight banks ? posted cas by programmable additive latency ? bust length: 4 with burst chop (bc) and 8. ? cas write latency (cwl): 5, 6, 7, 8 ? cas latency (cl): 6, 7, 8, 9, 10, 11 ? write latency (wl) =read latency (rl) - 1. ? bi - directional differential data strobe (dqs). ? data inputs on dqs centers when write. ? data outputs on dqs, /dqs edges when read. ? on chip dll align dq, dqs and /dqs transition with ck transition. ? dm mask write data - in at the both rising and falling edges of the data strobe. ? sequential & interleaved burst type available both for 8 & 4 with bc. ? multi purpose register (mpr) for pre - defined pattern read out ? on die termination (odt) options: synchronous odt, dynamic odt, and asynchronous odt ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms ? refresh interval: 7.8us t case between 0 c ~ 85 c ? refresh interval: 3 . 9 us t case between 85 c ~ 9 5 c ? rohs compliance ? pb - f ree ? driver strength: rzq/7, rzq/6(rzq=240 ) ? high temperature self - refresh rate enable ? zq calibration for dq drive and odt ? reset pin for initialization and reset function description the em 47 fm16 88 mca/sca is a high speed double date rate 3 (ddr3) low voltage synchronous dram fabricated with ultra high performance cmos process containing 8g(8,196m) bits which organized as 32 mb x 8 banks x 2 r by 16 bits. this synchronous device achieves high speed double - data - rate transfer rates of up to 1600 mb/sec/pin (ddr3 - 1600) for general applications. the chip is designed to comply with the following key ddr3 sdram features: (1) posted cas with additive latency, (2) write latency = read latency - 1, (3) on die termination, (4) programmable driver strength data,(5) seamless bl4 access with bank - grouping. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and /ck falling). all i/os are synchronized with a pair of bidirectional differential data strobes (dqs and /dqs) in a source synchronous fashion. the address bus is used to convey row, column and bank address information in a /ras and /cas multiplexing style. the 8 gb ddr3 devices operates with a single power supply: 1.35v - 0.065/+0.1v & 1.5v 0.075v vdd and vddq . available package: fbga - 96ball (with 0.8mm x 0.8mm ball pitch) jul. 2014 1/3 9 www.eorex.com
ordering information em 47 fm16 88 mca/sca part no organization max. freq package grade vdd/vddq em47 f m1688 mca - 150 512 m x 16 , 2r ddr3 l - 1333 (9 - 9 - 9) bga - 96b 10x13mm commercial 1.35v - 0.065/+0.1v em47 f m1688 mca - 150 a 512 m x 16 , 2r ddr3 l - 1333 (9 - 9 - 9) bga - 96b 10x14mm commercial 1.35v - 0.065/+0.1v em47 f m1688 mca - 1 25 512 m x 16 , 2r ddr3 l - 1 600 ( 11 - 11 - 11 ) bga - 96b 10x13mm commercial 1.35v - 0.065/+0.1v em47 f m1688 mca - 1 25a 512 m x 16 , 2r ddr3 l - 1 600 ( 11 - 11 - 11 ) bga - 96b 10x14mm commercial 1.35v - 0.065/+0.1v em47 f m1688 sca - 150 512 m x 16 , 2r ddr3 - 1333 (9 - 9 - 9) bga - 96b 10x13mm commercial 1.5v 0.075v em47 f m1688 sca - 150 a 512 m x 16 , 2r ddr3 - 1333 (9 - 9 - 9) bga - 96b 10x14mm commercial 1.5v 0.075v em47 f m1688 sca - 1 25 512 m x 16 , 2r ddr3 - 1 600 ( 11 - 11 - 11 ) bga - 96b 10x13mm commercial 1.5v 0.075v em47 f m1688 sca - 1 25a 512 m x 16 , 2r ddr3 - 1 600 ( 11 - 11 - 11 ) bga - 96b 10x1 4 mm commercial 1.5v 0.075v note: speed ( t ck *) is in order of cl - t rcd - t rp * eorex reserves the right to change products or specification without notice. jul. 2014 2/3 9 www.eorex.com
pin assignment: top view 96 ball fbga em 47 fm16 88 mca/sca jul. 2014 3/3 9 www.eorex.com 1 2 3 7 8 9 vddq dq13 dq15 a dq12 vddq vss vssq vdd vss b /udqs dq14 vssq vddq dq11 dq9 c udqs dq10 vddq vssq vddq udm d dq8 vssq vdd vss vssq dq0 e ldm vssq vddq vddq dq2 ldqs f dq1 dq3 vssq vssq dq6 /ldqs g vdd vss vssq vrefdq vddq dq4 h dq7 dq5 vddq odt 1 vss / ras j ck vss cke 1 odt 0 vdd / cas k /ck vdd cke 0 /cs 1 / cs 0 /we l a10 , ap zq 0 zq 1 vss ba0 ba2 m nc vrefca vss vdd a3 a0 n a12 , / bc ba1 vdd vss a5 a2 p a1 a4 vss vdd a7 a9 r a11 a6 vdd vss /reset a13 t a14 a8 vss
pin description (simplified) em 47 fm16 88 mca/sca jul. 2014 4/3 9 www.eorex.com pin name function j7,k7 ck, / ck (system clock) ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of / ck . output (read) data is referenced to the crossings of ck and / ck (both directions of crossing). l2 ,l1 / cs 0,1 (chip select) all commands are masked when / cs is registered high. / cs provides for external rank selection on systems with multiple ranks. / cs is considered part of the command code. k9 ,j9 cke 0,1 (clock enable) cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers. taking cke low provides precharge power - down and self - refresh operation (all banks idle), or active power - down (row active in any bank). cke is asynchronous for self refresh exit. after vrefca has become stable during the power on and initialization sequence, it must be maintained during all operations (including self - refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, / ck , odt and cke are disabled during power - down. input buffers, excluding cke, are disabled during self - refresh. n3,p7,p3,n2, p8,p2,r8,r2, t8,r3,l7,r7, n7,t3,t7 a0~a9,a10 ( ap ) , a11,a12( / bc ), a13,a14 (address) provided the row address (ra0 C ra1 5 ) for active commands and the column address (ca0 - ca9) and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). the address inputs also provide the op - code during mode register set commands. a12 is sampled during read and write commands to determine if burst chop (on - the - fly) will be performed. (high: no burst chop, low: burst chopped). see command truth table for details. m2,n8,m3 ba0, ba1,ba2 (bank address) ba0 C ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register is to be accessed during a mrs cycle. k1 ,j1 odt 0,1 (on die termination) odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is applied to each dq, dqs, / dqs , dmu and dml signal. the odt pin will be ignored if the mode register mr1 is programmed to disable odt.
pin description (continued) note: input pins only ba0 - ba2, a0 - a1 4 , / ras , / cas , / we , / cs , cke, odt and / reset do not supply em 47 fm16 88 mca/sca termination. jul. 2014 5/3 9 www.eorex.com c7,b7,f3,g3 udqs, udqs , ldqs , / ldqs (data strobe) output with read data, input with write data. edge - aligned with read data, centered in write data. ldqs corresponds to the data on dq0 - dq7; udqs corresponds to the data on dq8 - dq15. the data strobes ldqs, and udqs are paired with differential signals / udqs and / ldqs respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram supports differential data strobe only and does not support single - ended. j3, k3, l3 / ras , / cas , / we (command inputs) / ras , / cas & / we (along with / cs ) define the command being entered. d3,e7 udm,ldm (input data mask) udm & ldm are input mask signal for write data. input data is masked when udm or ldm are sampled high coincident with that input data during a write access. udm & ldm is sampled on both edges of udqs & ldqs respectively. d7,c3,c8,c2,a7, a2,b8,a3 dq0~7 (data input/output) data inputs and outputs are on the same pin. e3,f7,f2,f8,h3, h8,g2,h7 dq8~15 (data input/output) data inputs and outputs are on the same pin. b2,d9,g7,k2,k9,n 1,n9,r1,r9/a9,b3, e1,g8,j2,j8,m1,m 9,p1,p9,t1,t9 vdd / vss (power supply/ground) vdd and vss are power supply for internal circuits. a1,a8,c1,c9,d2,e 9,f1,h2,h9 /b1, b9,d1,d8,e2,e8, f9,g1,g9 vddq / vssq (dq power supply/dq ground) vddq and vssq are power supply for the output buffers. l8 , l9 zq 0, zq1 (zq calibration) reference pin for zq calibration t2 / reset (active low asynchronous reset) reset is active when / reset is low, and inactive when / reset is high. / reset must be high during normal operation. / reset is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v for dc low. h1 vrefdq (reference voltage) reference voltage for dq m8 vrefca (reference voltage) reference voltage for ca
absolute maximum rating note: caution exposing the device to stress above those listed in absolute maximum ratings recommended dc operating conditions single - ended ac and dc input levels for command and address single - ended ac and dc input levels for dq and dm note1. for input pins except /reset: vref= v refca (dc) or vref= v refdq (dc). em 47 fm16 88 mca/sca could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. note2. the ac peak noise on vref may not allow vref to deviate from v refca (dc) or vref= v refdq (dc) by more than 1% vdd (for reference: approx. 15mv. note3. for reference voltage = vdd/2 15mv. jul. 2014 6/3 9 www.eorex.com symbol parameter min. max. units v ihdq (dc100) dc input logic high vref+0.100 vdd v v ildq (dc100) dc input logic low vss vref - 0.100 v v ihdq (ac175) ac input logic high - - v v ildq (ac175) ac input logic low - - v v ihdq (ac150) ac input logic high vref+0.150 - v v ildq (ac150) ac input logic low - vref - 0.150 v v refdq (dc) reference voltage for dq, dm 0.49*vdd 0.51*vdd v symbol parameter min. max. units v ihca (dc100) dc input logic high vref+0.100 vdd v v ilca (dc100) dc input logic low vss vref - 0.100 v v ihca (ac175) ac input logic high vref+0.175 - v v ilca (ac175) ac input logic low - vref - 0.175 v v ihca (ac150) ac input logic high vref+0.150 - v v ilca (ac150) ac input logic low - vref - 0.150 v v refca (dc) reference voltage for add, cmd 0.49*vdd 0.51*vdd v symbol item rating units v in , v out input, output voltage - 0.4 ~ +1.975 v v dd power supply voltage - 0.4 ~ +1.975 v v ddq power supply voltage - 0.4 ~ +1.975 v t op operating temperature range commercial 0 ~ + 95 c industrial - 40 ~ + 9 5 t stg storage temperature range - 55 ~ +100 c symbol parameter min. typ. max. units v dd / v ddq power supply voltage / io voltage 1.283 1.35 1.45 v v dd / v ddq power supply voltage / io voltage 1. 425 1. 5 1. 575 v
pin capacitance notes1. vdd, vddq, vss, vssq applied and all other pins (except the pin under test) floating. vdd = vddq em 47 fm16 88 mca/sca =1.35v (1.5v) , vbias=vdd/2. notes2. absolute value of cck(ck - pin) - cck(/ck - pin). notes3 . cck (min.) will be equal to cin (min.) notes4. cdin_ctrl = cin_ctrl - 0.5*(cck(ck - pin) + cck(/ck - pin)) notes5 . cdin_add_cmd = cin_add_cmd - 0.5*(cck(ck - pin) + cck(/ck - pin)) notes6. although the dm, tdqs and /tdqs pins have different functions, the loading matches dq and dqs. notes7. dq should be in high impedance state. notes8. cdio = cio (dq, dm) - 0.5*(cio(dqs - pin) + cio(/dqs - pin)). notes9. maximum external load capacitance on zq pin is 5pf. notes10. absolute value of cio(dqs) - cio(/dqs). jul. 2014 7/3 9 www.eorex.com symbol parameters pins min. max. unit notes cck input pin capacitance, ck, /ck ck, /ck 0.8 1.4 pf 1,3 cdck delta input pin capacitance, ck, /ck 0 0.15 pf 1,2 cin_ctrl input pin capacitance, control pins /cs,cke,odt 0.75 1.3 pf 1 cdin_ctrl delta input pin capacitance, control pins - 0.4 0.2 pf 1,4 cin_add_cmd input pin capacitance, address and command pins /ras,/cas,/we, address 0.75 1.3 pf 1 cdin_add_cmd delta input pin capacitance, address and command pins - 0.4 0.4 pf 1,5 cio input/output pins capacitance dq,dqs,/dqs tdqs,/tdqs, dm 1.5 2.5 pf 1,6 cdio delta input/output pins capacitance - 0.5 0.3 pf 1,7,8 cddqs delta input/output pins capacitance dqs, /dqs 0 0.15 pf 1,10 czq input/output pin capacitance, zq zq - 3 pf 1,9
differential ac and dc input levels note1. it is used to define a differential signal slew - rate. em 47 fm16 88 mca/sca ac and dc logic input levels for differential signals differential signals definition note2. f or ck - /ck use vih/vil(ac) of address/command and vrefca; for strobes (dqs, dqs) use vih/vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note3. these values are not defined, however they single - ended signals ck, /ck, dqs, /dqs need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals. jul. 2014 8/3 9 www.eorex.com symbol parameter min. max. units note v ihdiff differential input high +0.2 see note3 v 1 v ildiff differential input low see note3 - 0.2 v 1 v ihdiff (ac) ac differential input high 2x(vih(ac) - vref) see note3 v 2 v ildiff (ac) ac differential input low see note3 2x(vref - vil(ac)) v 2
- allowed time before ringback (tdvac) for ck - /ck and dqs - /dqs em 47 fm16 88 mca/sca differential swing requirements for clock (ck - /ck) and strobe (dqs - /dqs) single - ended requirements for differential signals each individual component of a differential signal (ck, dqs, /ck, /dqs) has also to comply with certain requirements for single - ended signals. ck and /ck have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih(ac) / vil(ac) ) for address/command signals) in every half - cycle. dqs, /dqs have to reach vsehmin / vselmax [approximately the ac - levels (vih(ac) / vil(ac) ) for dq signals] in every half - cycle preceding and following a valid transition. note that the applicable ac - levels for address/command and dq?s might be different per speed - bin etc. e.g., if v ihca (ac150)/v ilca (ac150) is used for address/command signals, then these ac - levels apply also for the single - ended components of differential ck and /ck. jul. 2014 9/3 9 www.eorex.com slew rate [v/ns] tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv - min max min max >4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - <1.0 0 - 150 -
single - ended levels for ck, dqs, /ck, /dqs note1. for ck, /ck use vih/vil(ac) of address/command; for strobes (dqs, dqs) use vih/vil(ac) of dqs. em 47 fm16 88 mca/sca note that while address/command and dq signal requirements are with respect to vref, the single - ended components of differential signals have a requirement with respect to vdd/2; this is nominally the same. the transition of single - ended signals through the ac - levels is used to measure setup time. for singleended components of differential signals the requirement to reach vsel max, vseh min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. note2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for address/command is based on vrefca; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note3. these values are not defined, however the single - ended components of differential signals ck, /ck, dqs, /dqs need to be within the respective limits (vih(dc) max, vil(dc) min) for single - ended signals as well as the limitations for overshoot and undershoot. jul. 2014 10/3 9 www.eorex.com symbol parameter min. max. units note vseh single - ended high - level for strobes (vdd/2)+0.175 see note3 v 1,2 single - ended high - level for ck, /ck (vdd/2)+0.175 see note3 v 1,2 vsel single - ended low - level for strobes see note3 (vdd/2) - 0.175 v 1,2 single - ended low - level for ck, /ck see note3 (vdd/2) - 0.175 v 1,2
ac and dc output measurement levels notes1. the swing of 0.1 vddq is based on approximately 50% of the static single - ended output high or dqs output crossing voltage - vox (ddr3 - 1600 or higher speed bin) dqs output crossing voltage - vox (ddr3 - 1333 or lower speed bin) notes1. measured using an effective test load of 25 to 0.5* v ddq at each of the differential outputs. em 47 fm16 88 mca/sca low swing with a driver impedance of 34 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. notes2. the swing of 0.2 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 34 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. notes2. for a differential slew rate in between the listed values, the v ox value may be obtained by linear interpolation. notes3. the dqs, /dqs pins under test are not required to be able to drive each of the slew rates listed in the table; the pins under test will provide one v ox value when tested with specified test condition. the dqs and /dqs differential slew rate when measuring v ox determines which v ox limits to use. jul. 2014 11/3 9 www.eorex.com symbol parameter specification units note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8*v ddq v v om (dc) dc output middle measurement level (for iv curve linearity) 0.5*v ddq v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2*v ddq v v oh (ac) ac output high measurement level (for output slew rate) vtt+0.1*v ddq v 1 v ol (ac) ac output low measurement level (for output slew rate) vtt - 0.1*v ddq v 1 v ohdiff (dc) ac differential output high measurement level (for output slew rate) 0.2*v ddq v 2 v oldiff (dc) ac differential output low measurement level (for output slew rate) - 0.2*v ddq v 2 symbol parameters dqs, /dqs differential slew rate unit 5v/ns 6v/ns 7v/ns 8v/ns 9v/ns 10v/ns 11v/ns 12v/ns v ox (ac) max. deviation of dqs, /dqs output cross point voltage from 0.5*v ddq +100 +120 +140 +160 +180 +200 +200 +200 mv v ox (ac) min. - 100 - 120 - 140 - 160 - 180 - 200 - 200 - 200 mv symbol parameters dqs, /dqs differential slew rate unit 5v/ns 6v/ns 7v/ns 8v/ns 9v/ns 10v/ns 11v/ns 12v/ns v ox (ac) max. deviation of dqs, /dqs output cross point voltage from 0.5*v ddq +125 +150 +175 +200 +225 +225 +225 +225 mv v ox (ac) min. - 125 - 150 - 175 - 200 - 225 - 225 - 225 - 225 mv
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca recommended dc operating conditions jul. 2014 12/3 9 www.eorex.com symbol parameter & test conditions 1.35v 1.5v units 1333 1600 1333 1600 max max i dd 0 operating one bank active - to - precharge current: cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see timing used table; bl: 8; al: 0; /cs: high between act, rd and pre; command, address, data io: partially toggling; dm:stable at 0; bank activity: cycling with one bank active at a time; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 140 150 150 160 ma i dd1 operating one bank active - read - precharge current: cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see timing used table; bl: 8; al: 0; /cs: high between act, rd and pre; command, address, data io: partially toggling; dm:stable at 0; bank activity: cycling with one bank active at a time; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 190 200 210 220 ma i dd2p1 precharge power - down current fast exit: cke: low; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; /cs: stable at 1; command, address: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers; odt signal: stable at 0; pre - charge power down mode: fast exit 57 60 64 74 ma i dd2n precharge standby current: cke: high; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; /cs: stable at 1; command, address: partially toggling; data io: floating; dm:stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 80 90 90 100 ma i dd3p active power - down current: cke: low; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; /cs: stable at 1; command, address: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 75 80 80 90 ma i dd4w operating burst write current: cke: high; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; /cs: high between wr; command, address: partially toggling; data io: seamless write data burst with different data between one burst and the next one; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers; odt signal: stable at high 360 400 400 410 ma i dd4r operating burst read current: cke: high; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; /cs: high between rd; command, address: par - tially toggling; data io: seamless read data burst with different data between one burst and the next one; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 430 500 480 550 ma
em 47 fm16 88 mca/sca note 1 : burst length : bl8 fixed by mrs : set mr0 a[1,0]=00b note 2: output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2 ] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b note 3: precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit note 4: auto self - refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature note 5: self - refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range note 6: refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sdram note 7: read burst type : nibble sequential, set mr0 a[3]=0b jul. 2014 13/3 9 www.eorex.com symbol parameter & test conditions 1.35v 1.5v units 1333 1600 1333 1600 max max i dd5b burst refresh current: cke: high; external clock: on; tck, cl, nrfc: see timing used table; bl: 8; al: 0; /cs: high between ref; command, address: partially toggling; data io: floating; dm: stable at 0; bank activity: ref command every nrfc; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 380 40 0 41 0 43 0 ma i dd6 self refresh current: normal temperature range; tcase: 0 - 85c; auto self - refresh (asr): disabled; self - refresh temperature range (srt): normal; cke: low; external clock: off; ck and /ck: low; cl: see timing used table; bl: 8; al: 0; cs, command, address, data io: floating; dm: stable at 0; bank activity: self - refresh operation; output buffer and rtt: enabled in mode registers; odt signal: floating 40 40 45 45 ma i dd7 operating bank interleave read current; cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see timing used table; bl: 8; al: cl - 1; cs: high between act and rda; command, address: partially toggling; data io: read data bursts with different data between one burst and the next one; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 470 535 520 59 0 ma
em 47 fm16 88 mca/sca block diagram dm /reset zq odt auto/ self refresh counter a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 memory array s/ a & i/ o gating col. decoder dqm control clk, /clk clk, /clk dqs generator dll driver write fifo a12 a13 receiver ba0 ba1 col. add. buffer ba2 data in data out /clk mode register set col add. counter burst counter dio timing register dq[ 15 :0] clk cke /cs / ras / cas / we dm/tdqs /tdqs dqs,/dqs jul. 2014 14/3 9 www.eorex.com
vdd/vddq = 1.35v(1.283 - 1.45v) notes1. the cl setting and cwl setting result in tck (avg) (min.) and tck (avg) (max.) requirements. when em 47 fm16 88 mca/sca ac operating test characteristics ddr3 - 1333 & ddr3 - 1600 speed bins m aking a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. notes2. tck (avg) (min.) limits: since /cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating cl (nck) = taa (ns) / tck (avg)(ns), rounding up to the next ?supported cl?. notes3. tck (avg) (max.) limits: calculate tck (avg) + taa (max.)/cl selected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). this result is tck (avg) (max.) corresponding to cl selected. notes4. ?reserved? settings are not allowed. user must program a different value. notes5. any ddr3 - 1333 speed bin also supports functional operation at lower frequencies as shown in the table ddr3 - 1333 speed bins which is not subject to production tests but verified by design/characterization. notes6. any ddr3 - 1600 speed bin also supports functional operation at lower frequencies as shown in the table ddr3 - 1600 speed bins which is not subject to production tests but verified by design/characterization. notes7. trefi depends on operating case temperature (tc). notes8. for devices supporting optional down binning to cl = 7 and cl = 9, taa/trcd/trp(min.) must be 13.125 ns or lower. spd settings must be programmed to match. jul. 2014 15/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 150 (ddr3 - 1333) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t aa internal read command to first data 13.750 20 13.125 20 ns 8 t rcd active to read or write delay 13.750 - 13.125 - ns 8 t rp precharge command period 13.750 - 13.125 - ns 8 t rc active to active/auto refresh command 48.750 - 49.125 - ns 8 t ras active to precharge command period 35 9*t refi 36 9*t refi ns 7 t ck (avg) average clock cycle, cl=6, cwl=5 2.5 3.3 2.5 3.3 ns 1,2,3,5 .6 t ck (avg) average clock cycle, cl=7, cwl=6 1.875 <2.5 1.875 <2.5 ns 1,2,3,4 ,5,6 t ck (avg) average clock cycle, cl=8, cwl=6 1.875 <2.5 1.875 <2.5 ns 1,2,3,5 ,6 t ck (avg) average clock cycle, cl=9, cwl=7 1.5 <1.875 1.5 <1.875 ns 1,2,3,4 ,6 t ck (avg) average clock cycle, cl=10, cwl=7 1.5 <1.875 1.5 <1.875 ns 1,2,3,6 t ck (avg) average clock cycle, cl=11, cwl=8 1.25 <1.5 - - ns 1,2,3 - support cl settings 6,7,8,9,10,11 6,7,8,9,10 nck - support cwl settings 5,6,7,8 5,6,7 nck
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca ac operating test characteristics jul. 2014 16/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 150 (ddr3 - 1333) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t ck minimum clock cycle, dll - off mode 8 - 8 - ns 6 t ch , t cl (avg) average ck high/low level width 0.47 0.53 0.47 0.53 ns t rrd active bank a to active bank b command period 7.5 - 7.5 - ns 4 - 4 - nck t faw four activate window 4 0 - 45 - ns t ih (base) dc100 address and control input hold time (vih/vil(dc100) levels) 120 - 140 - ps 16 t is (base) ac175 address and control input setup time (vih/vil(ac175) levels) 45 - 65 - ps 16 t is (base) ac150 address and control input setup time (vih/vil(ac150) levels) 45+125 - 65+150 - ps 16,24 t dh (base) dq and dm input hold time (vih/vil(dc) levels) 45 - 65 - ps 17 t ds (base) dq and dm input setup time (vih/vil(ac) levels) 10 - 10 - ps 17 t ipw address and control input pulse width for each input 560 - 620 - ps 25 t dipw dq and dm input pulse width for each input 360 - 400 - ps 25 t hz (dq) dq high impedance time - 225 - 250 ps 13,14 t lz (dq) dq low impedance time - 450 225 - 500 250 ps 13,14 t hz (dqs) dqs,/dqs high impedance time rl+bl/2 reference - 225 - 250 ps 13,14 t lz (dqs) dqs,/dqs low impedance time rl - 1 reference - 450 225 - 500 250 ps 13,14 t dqsq dqs,/dqs to dq skew per group, per access - 100 - 125 ps 12,13 t ccd /cas to /cas command delay 4 - 4 - nck t qh dq output hold time from dqs, /dqs 0.38 - 0.38 - t ck (avg) 12,13 t dqsck dqs,/dqs rising edge output access time from rising ck,/ck - 225 225 - 255 255 ps 12,13 t dqss dqs latch rising transitions to associated clock edges - 0.27 0.27 - 0.25 0.25 t ck (avg) t dqsh dqs input high pulse width 0.45 0.55 0.45 0.55 t ck (avg) 27,28
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca ac operating test characteristics jul. 2014 17/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. ma x . min. max. t dsh dqs falling edge hold time from rising ck 0.18 - 0.2 - t ck (avg) 29 t dss dqs falling edge setup time to rising ck 0.18 - 0.2 - t ck (avg) 29 t dqsl dqs input low pulse width 0.45 0.55 0.45 0.55 t ck (avg) 26,28 t qsh dqs output high time 0.40 - 0.40 - t ck (avg) 12,13 t qsl dqs output low time 0.40 - 0.40 - t ck (avg) 12,13 t mrd mode register set command cycle 4 - 4 - nck t mod mode register set command update delay 15 - 15 - ns 12 - 12 - nck t rpre read preamble time 0.9 - 0.9 - t ck (avg) 13,19 t rpst read postamble time 0.3 - 0.3 - t ck (avg) 11,13 t wpre write preamble time 0.9 - 0.9 - t ck (avg) 1 t wpst write postamble time 0.3 - 0.3 - t ck (avg) 1 t wr write recovery time 15 - 15 - ns t dal (min) auto precharge write recovery + precharge time wr + roundup[t rp / t ck (avg) nck t mprr multi purpose register recovery time 1 - 1 - nck 22 t wtr internal write to read command delay 7.5 - 7.5 - ns 18 4 - 4 - nck t rtp internal read to precharge command delay 7.5 - 7.5 - ns 4 - 4 - nck t ckesr minimum cke low width for self - refresh entry to exit t cke (min) +1 - t cke (min) +1 - nck t cksre valid clock requirement after self - refresh entry or power - down entry 10 - 10 - ns 5 - 5 - nck t cksrx valid clock requirement before self - refresh exit or power - down exit 10 - 10 - ns 5 - 5 - nck
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca ac operating test characteristics ac operating test characteristics jul. 2014 18/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t xs exit self - refresh to commands not requiring a locked dll t rfc (min) + 10 - t rfc (min) + 10 - ns 5 - 5 - nck t xsdll exit self - refresh to commands requiring a locked dll t dll (min) - t dll (min) - nck t rfc auto - refresh to active/auto - refresh command 35 0 - 35 0 - ns t refi average periodic refresh interval 0 Q t c Q +85 - 7.8 - 7.8 s t cke cke minimum high and low pulse width 5 - 5.625 - ns 3 - 3 - nck t xpr exit reset from cke high to a valid command t rfc (min) + 10 - t rfc (min) + 10 - ns 5 - 5 - nck t dllk dll locking time 512 - 512 - nck t pd power - down entry to exit time t cke (min) 9*t refi t cke (min) 9*t refi 15 t xpdll exit precharge power - down with dll frozen to commands requiring a locked dll 24 - 24 - ns 2 10 - 10 - nck t xp exit power - down with dll on to any valid command; exit precharge power - down with dll frozen to commands not requiring a locked dll 6 - 6 - ns 3 - 3 - nck t wrpden (min) timing of wr command to power - down entry (bl8otf, bl8mrs, bl4otf) wl + 4 + [t wr / t ck (avg)] nck 9 t wrpden (min) timing of wr command to power - down entry (bc4mrs) wl + 2 + [t wr / t ck (avg)] nck t wrapden timing of wra command to power - down entry (bl8otf, bl8mrs, bl4otf) wl + 4 + wr + 1 - wl + 4 + wr + 1 - nck 10 t wrapden timing of wra command to power - down entry (bc4mrs) wl + 2 + wr + 1 - wl + 2 + wr + 1 - nck 10
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca jul. 2014 19/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. . min. max. t refpden timing of ref command to power - down entry 1 - 1 - nck 20,2 1 t mrspden timing of mrs command to power - down entry t mod (min) - t mod (min) - t cpded command pass disable delay 1 - 1 - nck t actpden timing of act command to power - down entry 1 - 1 - nck 20 t prpden timing of pre command to power - down entry 1 - 1 - nck 20 t rdpden timing of rd/rda command to power - down entry rl + 4 +1 - rl + 4 +1 - nck t aon rtt turn - on - 250 250 - 300 300 ps 7 t aonpd asynchronous rtt turn - on delay (power - down with dll frozen) 2 8.5 2 8.5 ns t aof rtt_nom and rtt_wr turn - off time from odtloff reference 0.3 0.7 0.3 0.7 t ck (avg) 8 t aofpd asynchronous rtt turn - off delay (power - down with dll frozen) 2 8.5 2 8.5 ns odth4 odt high time without write command or with write command and bc4 4 - 4 - nck odth8 odt high time with write command and bl8 6 - 6 - nck t adc rtt dynamic change skew 0.3 0.7 0.3 0.7 t ck (avg) t zqinit power - up and reset calibration time 512 - 512 - nck t zqoper normal operation full calibration time 256 - 256 - nck t zqcs normal operation short calibration time 64 - 64 - nck 23 t wlmrd first dqs pulse rising edge after write leveling mode is programmed 40 - 40 - nck 3 t wldqsen dqs./dqs delay after write leveling mode is programmed 25 - 25 - nck 3 t rtw read to write command delay (bc4mrs, bc4otf) rl + t ccd /2 + 2nck - wl - rl + t ccd /2 + 2nck - wl - t rtw read to write command delay (bl8mrs, bl8otf) rl + t ccd /2 + 2nck - wl - rl + t ccd /2 + 2nck - wl - t rap active to read with auto precharge command delay t rcd min - t rcd min -
vdd/vddq = 1.35v(1.283 - 1.45v) em 47 fm16 88 mca/sca ac operating test characteristics jul. 2014 20/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t wls write leveling setup time from rising ck,/ck crossing to rising dqs,/dqs crossing 165 - 195 - ps t wlh write leveling hold time from rising dqs,/dqs crossing to rising ck,/ck crossing 165 - 195 - ps t wlo write leveling output delay 0 7.5 0 9 ns t wloe write leveling output error 0 2 0 2 ns t ck (abs) absolute clock period t ck (avg)min+ t jit (per)min t ck (avg)max+ t jit (per)max t ck (avg)min+ t jit (per)min t ck (avg)max+ t jit (per)max ps t ch (abs) absolute clock high pulse width 0.43 - 0.43 - t ck (avg) 30 t cl (abs) absolute clock low pulse width 0.43 - 0.43 - t ck (avg) 31 t jit (per) clock period jitter - 70 70 - 80 80 ps t jit (per,lck) clock period jitter during dll locking period - 60 60 - 70 70 ps t jit (cc) cycle to cycle period jitter - 140 - 160 ps t jit (cc,lck) cycle to cycle period jitter during dll locking period - 120 - 140 ps t err (2per) cumulative error across 2 cycles - 103 103 - 118 118 ps t err (3per) cumulative error across 3 cycles - 122 122 - 140 140 ps t err (4per) cumulative error across 4 cycles - 136 136 - 155 155 ps t err (5per) cumulative error across 5 cycles - 147 147 - 168 168 ps t err (6per) cumulative error across 6 cycles - 155 155 - 177 177 ps t err (7per) cumulative error across 7 cycles - 163 163 - 186 186 ps t err (8per) cumulative error across 8 cycles - 169 169 - 193 193 ps t err (9per) cumulative error across 9 cycles - 175 175 - 200 200 ps t err (10per) cumulative error across 10 cycles - 180 180 - 205 205 ps t err (11per) cumulative error across 11 cycles - 184 184 - 210 210 ps t err (12per) cumulative error across 12 cycles - 188 188 - 215 215 ps t err (nper) cumulative error across n= 13,14, 49,50 cycles t err (nper)min=(1+0.68ln(n))*t jit (per)min t err (nper)max=(1+0.68ln(n))*t jit (per)max ps 32
vdd/vddq = 1.35v(1.283 - 1.45v) note 1: actual value dependant upon measurement level definitions which are tbd. em 47 fm16 88 mca/sca ac operating test characteristics note 2: commands requiring a locked dll are: read (and reada) and synchronous odt commands. note 3: the max values are system dependent. note 4: wr as programmed in mode register. note 5: value must be rounded - up to next higher integer value. note 6: there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. note 7: odt turn on time (min.) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time (max.) is when the odt resistance is fully on. both are measured from odtlon. note 8: odt turn - off time (min.) is when the device starts to turn - off odt resistance. odt turn - off time (max.) is when the bus is in high impedance. both are measured from odtloff. note 9: twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. note 10: wr in clock cycles as programmed in mr0. note 11: the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. note 12: output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. note 13: value is only valid for ron34. note 14: single ended signal parameter. refer to the section of tlz(dqs), tlz(dq), thz(dqs), thz(dq) notes for definition and measurement method. note 15: trefi depends on operating case temperature (tc). note 16: tis(base) and tih(base) values are for 1v/ns command/ addresss single - ended slew rate and 2v/ns ck, /ck differential slew rate, note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset, vref(dc) = vrefca(dc). see address / command setup, hold and derating section. note 17: tds(base) and tdh(base) values are for 1v/ns dq single - ended slew rate and 2v/ns dqs, /dqs differential slew rate. note for dq and dm signals, vref(dc)= vrefdq(dc). for input only pins except reset, vref(dc) = vrefca(dc). see data setup, hold and and slew rate derating section. jul. 2014 21/3 9 www.eorex.com symbol speed bin - 125 (ddr3 - 1600) - 150 (ddr3 - 1333) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t anpd odt to power - down entry/ exit latency wl C 1 - wl C 1 - nck odtl on odt turn on latency wl C 2 wl C 2 wl C 2 wl C 2 nck odtl off odt turn off latency wl C 2 wl C 2 wl C 2 wl C 2 nck odtl cnw odt latency for changing from rtt_nom to rtt_wr wl C 2 wl C 2 wl C 2 wl C 2 nck odtl cwn4 odt latency for changing from rtt_wr to rtt_nom (bc4) - 4+odtl off - 4+odtl off nck odtl cwn8 odt latency for changing from rtt_wr to rtt_nom (bl8) - 6+odtl off - 6+odtl off nck
em 47 fm16 88 mca/sca note 18: start of internal write transaction is defined as follows ; for bl8 (fixed by mrs and on - the - fly, otf) : rising clock edge 4 clock cycles after wl. for bc4 (on - the - fly, otf) : rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl. note 19: the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side. note 20: cke is allowed to be registered low while operations such as row activation, precharge, auto precharge or refresh are in progress, but power - down idd spec will not be applied until finishing those operation. note 21: although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. note 22: defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. note 23: one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity and odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. note 24: the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. note 25: pulse width of a input signal is defined as the width between the first crossing of vref(dc) and the consecutive crossing of vref(dc). note 26: tdqsl describes the instantaneous differential input low pulse width on dqs - /dqs, as measured from one falling edge to the next consecutive rising edge. note 27: tdqsh describes the instantaneous differential input high pulse width on dqs - /dqs, as measured from one rising edge to the next consecutive falling edge. note 28: tdqsh,act + tdqsl,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. note 29: tdsh,act + tdss,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. note 30: tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. note 31: tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. note 32: n = from 13 cycles to 50 cycles. this row defines 38 parameters. jul. 2014 22/3 9 www.eorex.com
em 47 fm16 88 mca/sca simplified state diagram jul. 2014 23/3 9 www.eorex.com
1. command truth table h = high level, l = low level, x = don't care, v = valid, ba=bank address, ca=column address, ra=row address em 47 fm16 88 mca/sca jul. 2014 24/3 9 www.eorex.com command symbol cke /cs /ras /cas /we ba0~ ba2 a10 a12, a10~a0 n - 1 n device deselect des h h h x x x x x x,x no operation nop h h l h h h v v v,v read (fixed bl8/bc4) rd h h l h l h ba l v,ca read (bc4, otf) rds4 h h l h l h ba l l,ca read (bl8, otf) rds8 h h l h l h ba l h,ca read with auto pre - charge (fixed bl8/bc4) rda h h l h l h ba h v,ca read with auto pre - charge (bc4, otf) rdas4 h h l h l h ba h l,ca read with auto pre - charge (bl8, otf) rdas8 h h l h l h ba h h,ca write (fixed bl8/bc4) wr h h l h l l ba l v,ca write (bc4, otf) wrs4 h h l h l l ba l l,ca write (bl8,otf) wrs8 h h l h l l ba l h,ca write with auto pre - charge (fixed bl8/bc4) wra h h l h l l ba h v,ca write with auto pre - charge (bc4, otf) wras 4 h h l h l l ba h l,ca write with auto pre - charge (bl8, otf) wras 8 h h l h l l ba h h,ca bank activate act h h l l h h ba ra pre - charge single bank pre h h l l h l ba l v,v pre - charge all banks prea h h l l h l v h v,v mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v,v self refresh entry sre h l l l l h v v v,v self refresh exit srx l h h x x x x x x,x l h h h v v v,v power down entry pde h l h x x x x x x,x h l l h h h v v v,v power down exit pdx l h h x x x x x x,x l h l h h h v v v,v zq calibration long zqcl h h l h h l x h x,x zq calibration short zqcs h h l h h l x l x,x
em 47 fm16 88 mca/sca note1. all ddr3 sdram commands are defined by states of /cs, /ras, /cas, /we and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. note2. /reset is low enable command which will be used only for asynchronous reset so must be maintained high during any function. note3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. note4. v means h or l (but a defined logic level) and x means either defined or undefined (like floating) logic level. note5. burst reads or writes cannot be terminated or interrupted and fixed/on - the - fly (otf) bl will be defined by mrs. note6. the power down mode does not perform any refresh operation. note7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. note8. self refresh exit is asynchronous. note9. vref(both vrefdq and vrefca) must be maintained during self refresh operation. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh. note10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3 sdram from registerng any unwanted commands between operations. a no operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. note11. the deselect command performs the same function as no operation command. note12. refer to the cke truth table for more detail with cke transition. jul. 2014 25/3 9 www.eorex.com
2. cke truth table note1. cke (n) is the logic state of cke at clock edge n; cke (n - 1) was the state of cke at the previous clock em 47 fm16 88 mca/sca edge. note2. current state is defined as the state of the ddr3 sdram immediately prior to clock edge n. note3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. note4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. note5. the state of odt does not affect the states described in this table. the odt function is not available during self - refresh. note6. during any cke transition (registration of cke h - >l or cke l - >h) the cke level must be maintained until 1nck prior to tckemin being satisfied (at which time cke may transition again). note7. deselect and nop are defined in the command truth table. note8. on self - refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after txsdll is satisfied. note9. self - refresh mode can only be entered from the all banks idle state. note10. must be a legal command as defined in the command truth table. note11. valid commands for power - down entry and exit are nop and deselect only. note12. valid commands for self - refresh exit are nop and deselect only. note13. self - refresh can not be entered during read or write operations. note14. the power - down does not perform any refresh operations. note15. x means don?t care (including floating around vref) in self - refresh and power - down. it also applies to address pins. note16. vref (both vrefdq and vrefca) must be maintained during self - refresh operation. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refresh jul. 2014 26/3 9 www.eorex.com current state cke command (n) /ras, /cas, /we, /cs action (n) notes n - 1 n power down l l x maintain power down 14,15 l h deselect or nop power down exit 11,14 self refresh l l x maintain self refresh 15,16 l h deselect or nop self refresh exit 8,12,16 bank active h l deselect or nop active power down entry 11,13,14 reading h l deselect or nop power down entry 11,13,14,17 writing h l deselect or nop power down entry 11,13,14,17 precharging h l deselect or nop power down entry 11,13,14,17 refreshing h l deselect or nop precharge power down entry 11 all banks idle h l deselect or nop precharge power down entry 11,13,14,18 h l refresh self refresh 9,13,18 for more details with all signals, see command truth table 10
em 47 fm16 88 mca/sca operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh. note17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power - down is entered, otherwise active power - down is entered. note18. ?idle state? is defined as all banks are closed (trp, tdal, etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) as well as all self - refresh exit and power - down exit parameters are satisfied (txs, txp, txpdll, etc). jul. 2014 27/3 9 www.eorex.com
em 47 fm16 88 mca/sca initialization the following sequence is required for power - up and initialization and is shown in below figure: 1. apply power (/reset is recommended to be maintained below 0.2 x vdd; all other inputs may be undefined). /reset needs to be maintained for minimum 200 us with stable power. cke is pulled low anytime before /reset being de - asserted (min. time 10 ns). the power voltage ramp time between 300 mv to vddmin must be no greater than 200 ms; and during the ramp, vdd > vddq and (vdd - vddq) < 0.3 volts. ? vdd and vddq are driven from a single power converter output, and ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95 v max once power ramp is finished, and ? vref tracks vddq/2. or ? apply vdd without any slope reversal before or at the same time as vddq. ? apply vddq without any slope reversal before or at the same time as vtt & vref. ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after /reset is de - asserted, wait for another 500 us until cke becomes active. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clocks (ck, /ck) need to be started and stabilized for at least 10 ns or 5 t ck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (t is ) must be met. also, a nop or deselect command must be registered (with t is set up time to clock) before cke goes active. once the cke is registered high after reset, cke needs to be continuously registered high until the initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3 sdram keeps its on - die termination in high - impedance state as long as /reset is asserted. further, the sdram keeps its on - die termination in high impedance state after /reset de - assertion until cke is registered high. the odt input signal may be in undefined state until t is before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is finished, including the expiration of tdllk and tzqinit. 5. after cke is being registered high, wait minimum of reset cke exit time, t xpr , before issuing the first mrs command to load mode register. (t xpr =max (t xs ; 5 x t ck ) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2 , provide low to ba0 and ba2, high to ba1.) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3 , provide low to ba2, high to ba0 and ba1.) 8. issue mrs command to load mr1 with all application settings and dll enabled. (to issue "dll enable" jul. 2014 28/3 9 www.eorex.com
em 47 fm16 88 mca/sca command, provide "low" to a0, "high" to ba0 and "low" to ba1 C ba2). 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll reset command, provide "high" to a8 and "low" to ba0 - 2). 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. reset and power up initialization sequence jul. 2014 29/3 9 www.eorex.com
controlling the states of address pins according to the table below. em 47 fm16 88 mca/sca mode register definition mode register mr0 the mode register mr0 stores the data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr and dll control for precharge power - down, which include various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on /cs, /ras, /cas, /we, ba0, ba1 and ba2, while read burst type nibble sequential interleave a3 0 1 note1. ba2 and a13 are reserved for future use and must be programmed to 0 during mrs. note2. wr (write recovery for autoprecharge) min in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wrmin[cycles] = roundup(t wr [ns]/t c k[ns]). the wr value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with t rp to determine t dal . jul. 2014 30/3 9 www.eorex.com wr for autoprecharge a11 a10 a9 reserved 0 0 0 5 0 0 1 6 0 1 0 7 0 1 1 8 1 0 0 10 1 0 1 12 1 1 0 reserved 1 1 1 cas latency a6 a5 a4 a2 reserved 0 0 0 0 reserved 0 0 1 0 6 0 1 0 0 7 0 1 1 0 8 1 0 0 0 9 1 0 1 0 10 1 1 0 0 11 1 1 1 0 ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 00 0 ppd wr dll tm cas latency rbt cl bl mrs mode ba1 ba0 mr0 0 0 mr1 0 1 mr2 1 0 mr3 1 1 bl a1 a0 8 0 0 4 or 8 (otf) 0 1 4 1 0 reserved 1 1 dll control (for precharge pd) a12 slow exit (dll off) 0 fast exit (dll on) 1 dll reset a8 no 0 yes 1 mode a7 normal 0 test 1
burst type (a3) note1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock em 47 fm16 88 mca/sca cycles earlier than for the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being selected on - the - fly via a12 (/bc), the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - fly control, the starting point for twr and twtr will not be pulled in by two clocks. note2. 0...7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. note3. t: output driver for data and strobes are in high impedance. note4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. note5. x: don?t care. jul. 2014 31/3 9 www.eorex.com burst length r/w a2 a1 a0 sequential addressing, a3=0 interleave addressing, a3=1 4 (chop) r 0 0 0 0123tttt 0123tttt r 0 0 1 1230tttt 1032tttt r 0 1 0 2301tttt 2301tttt r 0 1 1 3012tttt 3210tttt r 1 0 0 4567tttt 4567tttt r 1 0 1 5674tttt 5476tttt r 1 1 0 6745tttt 6745tttt r 1 1 1 7456tttt 7654tttt w 0 v v 0123xxxx 0123xxxx w 1 v v 4567xxxx 4567xxxx 8 r 0 0 0 01234567 01234567 r 0 0 1 12305674 10325476 r 0 1 0 23016745 23016745 r 0 1 1 30127456 32107654 r 1 0 0 45670123 45670123 r 1 0 1 56741230 54761032 r 1 1 0 67452301 67452301 r 1 1 1 74563012 76543210 w v v v 01234567 01234567
em 47 fm16 88 mca/sca cas latency the cas latency is defined by mr0 (bits a9 - a11). cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half - clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. test mode the normal operating mode is selected by mr0 (bit a7 = 0) and rest bits set to the desired values. programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram factory and should not be used. no operations or functionality is specified if a7 = 1. dll reset the dll reset bit is self - clearing, meaning that it returns back to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time that the dll reset function is used, tdllk must be met before any functions that require the dll can be used (i.e., read commands or odt synchronous operations). write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal. wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns]/ tck[ns]). the wr must be programmed to be equal to or larger than twr(min). precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12 = 0), or ?slow - exit?, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or ?fast - exit?, the dll is maintained after entering precharge power - down and upon exiting power - down requires txp to be met prior to the next valid command. jul. 2014 32/3 9 www.eorex.com
em 47 fm16 88 mca/sca mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on /cs, /ras, /cas, /we, high on ba0, low on ba1 and ba2, while controlling the states of address pins according to the table below. note1. ba2, a8, a10 and a13 are reserved for future use (rfu) and must be programmed to 0 during mrs. note2. qoff: outputs disabled - dqs, dqss, /dqss. note3. in write leveling mode ( mr1 [bit7] = 1) with mr1 [bit12] = 1, all rtt_nom settings are allowed; in write leveling mode ( mr1 [bit7] = 1) with mr1 [bit12] = 0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. note4. new ron value is defined as ron48=rzq/5. jul. 2014 33/3 9 www.eorex.com ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 01 0 qoff tdqs 0 rtt 0 level rtt d.i.c al rtt d.i.c dll rtt_nom a9 a6 a2 odt disabled 0 0 0 rzq/4 0 0 1 rzq/2 0 1 0 rzq/6 0 1 1 rzq/12 1 0 0 rzq/8 1 0 1 reserved 1 1 0 reserved 1 1 1 output driver impedance control a5 a1 rzq/6 0 0 rzq/7 0 1 reserved 1 0 reserved 1 1 additive latency a4 a3 0 0 0 cl - 1 0 1 cl - 2 1 0 reserved 1 1 mrs mode ba1 ba0 mr0 0 0 mr1 0 1 mr2 1 0 mr3 1 1 qoff a12 output buffer enabled 0 output buffer disabled 1 write leveling enable a8 disabled 0 enabled 1 tdqs enable a11 disabled 0 enabled 1 dll enable a0 enable 0 disable 1
em 47 fm16 88 mca/sca dll enable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0 = 0), the dll is automatically disabled when entering self - refresh operation and is automatically re - enabled upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation, except when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed information on dll disable operation refers to dll - off mode. the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1 {a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. odt rtt values ddr3 sdram is capable of providing two different termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1 . a separate value (rtt_wr) may be programmed in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is disabled. additive latency additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidths in ddr3 sdram. in this operation, it allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. jul. 2014 34/3 9 www.eorex.com
em 47 fm16 88 mca/sca write leveling for better signal integrity, ddr3 memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has the benefit of reducing the number of stubs and their length, but it also causes flight time skew between clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdram supports a ?write leveling? feature to allow the controller to compensate for skew. output disable the outputs may be enabled/disabled by mr1 (bit a12). when this feature is enabled (a12 = 1), all output pins (dqs, dqs, /dqs, etc.) are disconnected from the device, thus removing any loading of the output drivers. for normal operation, a12 should be set to ?0?. tqs, /tdqs tdqs (termination data strobe) provides additional termination resistance outputs that may be useful in some system configurations. when enabled via the mode register, the same termination resistance function is applied to the tdqs & /tdqs pins that is applied to the dqs & /dqs pins. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided and the /tdqs pin is not used. jul. 2014 35/3 9 www.eorex.com
on ba1, low on ba0 and ba2, while controlling the states of address pins according to the table below. note1. ba2, a8, a11 ~ a13 are rfu and must be programmed to 0 during mrs. em 47 fm16 88 mca/sca mode register mr2 the mode register mr2 stores the data for controlling refresh related features, including rtt_wr impedance and cas write latency (cwl). the mode register 2 is written by asserting low on /cs, /ras, /cas, /we, high note2. the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not available. cas write latency (cwl) the cas write latency is defined by mr2 (bits a3 - a5). cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3 sdram does not support any half - clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl = al + cwl. dynamic odt (rtt_wr) ddr3 sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. jul. 2014 36/3 9 www.eorex.com cas write latency (cwl) a6 a4 a3 5( t R 2.5 ns) ck 0 0 0 6 (2.5ns t R 1 .875ns) ck 0 0 1 7 (1.875ns t R 1 .5ns) ck 0 1 0 8 (1.5ns t R 1 .25ns) ck 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 0 0 0 rtt_wr 0 srt 0 cwl 0 rtt_wr a10 a9 dynamic odt off 0 0 rzq/4 0 1 rzq/2 1 0 reserved 1 1 mrs mode ba1 ba0 mr0 0 0 mr1 0 1 mr2 1 0 mr3 1 1 self refresh temp. range a7 normal operating temp. range 0 extended temp. self refresh 1
em 47 fm16 88 mca/sca mode register mr3 the mode register mr3 controls multi purpose registers (mpr). the mode register 3 is written by asserting low on cs, ras, cas, we, high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the table below. note1. ba2, a3 - a13 are reserved for future use (rfu) and must be programmed to 0 during mrs. note2. the predefined pattern will be used for read synchronization. note3. when mpr control is set for normal operation, mr3 a[2] = 0, mr3 a[1:0] will be ignored multi purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled ( mr3 bit a2 = 0). power - down mode, self - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. jul. 2014 37/3 9 www.eorex.com ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 mpr mpr location mpr location a1 a0 predefined pattern 0 0 reserved 0 1 reserved 1 0 reserved 1 1 mrs mode ba1 ba0 mr0 0 0 mr1 0 1 mr2 1 0 mr3 1 1 mpr operation a2 normal operation 0 dataflow from mpr 1
em 47 fm16 88 mca/sca package description: 96 ball - fbga solder ball: lead free (sn - ag - cu) jul. 2014 38/3 9 www.eorex.com
em47fm1688mca/sca package description: 96 ball - fbga solder ball: lead free (sn - ag - cu) jul. 2014 3 9 /3 9 www.eorex.com

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